Glossary

Controller architecture

Reserve phase

Instruction processing that prepares and enqueues time points and their events.

Trigger phase

Release of queued events at their scheduled time points. See eQASM, Section 3.1.

TCU

The timing control unit: timing queue, per-port event queues and timing controller. See QuMA, Section 5.2.

BISP

The booking-based synchronization protocol from Distributed-HISQ, Section 4.1. A controller sends a signal to its neighbor and starts a countdown equal to its configured outgoing link delay. Synchronization completes when both the countdown has expired and the neighbor’s signal has arrived.

Time point

A point on the logical TCU timeline at which zero or more events are scheduled. The CPU prepares time points independently of the TCU timer.

Timing queue

A FIFO of time points, each specifying an interval from the preceding point.

Per-port event queue

A FIFO of events for one output port, ordered by time point.

Port and codeword

A cw instruction selects a mapping by source port and codeword. The mapping specifies one or more output ports and their operations.

Enqueue

Insertion of a time point and all its events into the TCU queues together.

Event trigger

Release of the events for a due time point. Each output starts after its configured delay.

Readout

Acquisition, discrimination and delivery of a measurement result.

Acquisition

A measurement interval. The backend samples at its end.

Discrimination

Conversion of a readout signal into a bit. qsbit-sim models its timing through discriminator_delay; the backend supplies the bit and may model readout physics.

Discriminator arm

An event that enables discrimination for a specific acquisition. When separate_arm is enabled, a DiscriminatorArmSpec event must match the acquisition’s target and measurement reference. Otherwise the discriminator is armed at acquisition start. See readout timing.

Classical feedback

Reading a measurement result into the CPU and using program control flow to select subsequent operations.

Fast conditional execution

Executing or canceling a single-qubit operation at its trigger edge according to the target qubit’s selected execution flag.

Measurement result register

One bit per qubit, read by fmr. A pending count prevents reads until all accepted measurements of that qubit complete.

Execution flag

Per-qubit state used to evaluate measurement-dependent execution conditions: last_one, last_zero and equal. The always condition requires no measurement state.

Simulation time and scheduling

SystemC

The C++ discrete-event simulation library that schedules model execution.

Simulation time

Time in the modeled system, measured in nanoseconds. It continues across resets.

Host time

Elapsed execution time on the computer running the simulator.

Tick

A one-nanosecond unit of simulation time. Tick represents physical time; TcuCycle represents logical TCU cycles. See field units.

Clock period and phase

Period is the interval between rising edges. Phase is the first rising edge’s offset from time zero. Edges occur at phase + k * period.

TCU logical cycle

When the TCU is not paused, cycle n occurs at epoch_start + n * tcu.period + paused_ticks, where paused_ticks is the accumulated pause duration. Each paused edge shifts subsequent logical cycles by one TCU period. Synchronization and an empty queue after wait 0 can pause the timer. Initially, epoch_start is profile.start and paused_ticks is zero; reset calculates a new start.

Arrival time

The earliest receiver edge at which a published message can be consumed. The mailbox stores it in eligible.

Mailbox

A bounded FIFO that retains messages until consumption. A message becomes readable at its configured receiver-edge arrival time.

Elaboration

Construction of SystemC modules, processes and connections before simulation.

Initialization

The initial SystemC kernel phase. dont_initialize() suppresses automatic process invocation; an event at time zero can still trigger the process.

Sensitivity

The events that make a SystemC process runnable.

Delta cycle

A scheduling round that does not advance simulation time.

Device barrier

Simulator::barrier(), which processes device events after all clocked methods due at the same tick have finished.

Trigger tick and start tick

The trigger tick is the simulation time when the TCU releases an event. The start tick is when its physical operation begins: trigger_tick + delay.

Physical boundary

A tick with scheduled output starts, ends, measurement samples or ready results.

Programs and CPU execution

RV32I

The base 32-bit RISC-V integer instruction set. qsbit-sim adds custom-0 control instructions and custom-1 bundles.

ISA and microarchitecture

The ISA defines instruction encodings and effects. The microarchitecture defines how they execute, including pipeline stages, stalls and timing.

CPU pipeline

Fetch, decode and execute stages. Each instruction advances at most one stage per CPU edge. Execute also commits its result.

Stall

An unfinished instruction retains its state until a later CPU edge retries it.

Speculative instruction

An instruction fetched before older control flow or faults are resolved. Only the oldest instruction can issue stores or control operations.

Program image

Executable bytes, segment permissions and entry address loaded from ELF or raw machine code.

Simulator records and checks

Timing label

An identifier that associates a time point with its event-queue entries.

Timing and event records

TimingEvents carries a time point and its events. EnqueueReply acknowledges insertion. TriggeredEvents carries the events selected at a trigger edge.

Measurement reference

MeasurementReference identifies a pending delivery by epoch, measurement ID and target qubit.

Measurement storage

MeasurementRegisters stores per-qubit result bits and pending counts. ExecutionFlags stores per-qubit flags for trigger-time checks.

Resource

A configured ID used to detect conflicting output intervals. Overlapping intervals sharing an ID conflict if either requires exclusive use.

Event specification

EventSpec defines an operation’s output parameters. ScheduledEvent stores the event, start and end ticks, and the resolved EventSpec in resolved. The operation occupies [start, end).

Quantum backend

An implementation of IQuantumBackend that supplies quantum-state evolution, measurement outcomes, or both. The mock backend supplies fixed outcomes without a quantum state.

Ideal gate and pulse drive

An ideal gate changes state at its start. A pulse drive contributes to evolution throughout its interval.

Configuration and completion

Run configuration

A JSON file selecting the program, backend, profile and outputs. Paths resolve relative to the file’s directory.

Simulation profile

Clock periods, delays, capacities and codeword mappings fixed for a run. Each core can have its own profile overlay. All cores share the TCU clock, qubit count, seed, watchdog and two-qubit gate definitions.

Drain

Completion of pending events, memory transactions, result deliveries, decoder work and synchronization across all cores after their exit ECALLs.

Session reset

A new epoch with all cores, the synchronization network, the decoder system and the backend reset. Memory and profiles are preserved.

Trace record

A timestamped observation with event-specific fields. See trace formats.

Watchdog

The global simulation deadline. The run fails if it has not drained when the deadline is checked.