Simulator component reference#

Each component page describes its inputs, outputs, state, errors and tests. The implementation map shows their connections. See simulation timing for edge order and communication delays.

Setup and CPU#

Module

What it does

Platform and clocks

Creates the simulation profile, clocks and scheduled wakeups.

ELF loader

Loads executable bytes, segment permissions and entry PC.

ISA decoder

Decodes instructions and calculates architectural effects.

CPU cycle model

Advances the pipeline, handles stalls and retires instructions.

Memory

Completes timed fetches, loads and stores.

Quantum instruction adapter

Converts instruction fields and operands into control operations.

Command preparation and TCU#

Module

What it does

Port and codeword mapping

Selects device events from the simulation profile.

Codeword decoding

Expands commands into identified per-port events.

Reserve phase

Prepares events at a time point and requests queue insertion.

Communication latency and enqueue

Transfers requests and inserts timing and event entries together.

Timing queue

Retains intervals, due cycles and member lists.

Per-port event queues

Retain events until their time point’s label triggers.

TCU timer

Selects the due time point on each TCU edge.

Conditional execution checks

Checks execution flags and validates the selected events.

Devices, feedback and completion#

Module

What it does

Control output and resource checks

Reserve and execute physical intervals.

Quantum backend

Supplies quantum-state evolution, measurement outcomes, or both.

Acquisition and discrimination

Samples measurements and schedules result readiness.

Measurement result registers

Stores per-qubit bits and pending measurement counts for FMR.

Execution flags

Updates per-qubit flags used at the trigger edge.

Tracing and completion

Records observations and distinguishes complete drain from failure.

Synchronization

Synchronizes neighboring controllers using timed booking signals.

Decoder transport and processing

Transfers syndrome bits, schedules decoding jobs and returns corrections through MMIO.

Run a component’s named tests with ctest --test-dir BUILD_DIRECTORY -R NAME. Numerical tests require the corresponding build options.