Simulator component reference#
Each component page describes its inputs, outputs, state, errors and tests. The implementation map shows their connections. See simulation timing for edge order and communication delays.
Setup and CPU#
Module |
What it does |
|---|---|
Creates the simulation profile, clocks and scheduled wakeups. |
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Loads executable bytes, segment permissions and entry PC. |
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Decodes instructions and calculates architectural effects. |
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Advances the pipeline, handles stalls and retires instructions. |
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Completes timed fetches, loads and stores. |
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Converts instruction fields and operands into control operations. |
Command preparation and TCU#
Module |
What it does |
|---|---|
Selects device events from the simulation profile. |
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Expands commands into identified per-port events. |
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Prepares events at a time point and requests queue insertion. |
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Transfers requests and inserts timing and event entries together. |
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Retains intervals, due cycles and member lists. |
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Retain events until their time point’s label triggers. |
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Selects the due time point on each TCU edge. |
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Checks execution flags and validates the selected events. |
Devices, feedback and completion#
Module |
What it does |
|---|---|
Reserve and execute physical intervals. |
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Supplies quantum-state evolution, measurement outcomes, or both. |
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Samples measurements and schedules result readiness. |
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Stores per-qubit bits and pending measurement counts for FMR. |
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Updates per-qubit flags used at the trigger edge. |
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Records observations and distinguishes complete drain from failure. |
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Synchronizes neighboring controllers using timed booking signals. |
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Transfers syndrome bits, schedules decoding jobs and returns corrections through MMIO. |
Run a component’s named tests with ctest --test-dir BUILD_DIRECTORY -R NAME.
Numerical tests require the corresponding build options.