ISA decoder and semantics#

The ISA library decodes instruction words and calculates their architectural effects. It specifies the result of an instruction; the CPU model decides when that result becomes visible.

Connections#

  • Input: a 32-bit instruction word for rv32::decode(); a decoded instruction, PC and operand values for rv32::evaluate().

  • Output: rv32::Decoded and rv32::Effect values, or a typed fault.

  • Caller: the CPU model’s decode and execute stages.

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Decode and evaluate#

decode() identifies RV32I and custom-0 instructions, checks fixed encoding bits, and extracts registers and immediates.

The VLIW CPU decodes custom-1 bundles with decode_cw_bundle().

evaluate() calculates arithmetic results, branch decisions, the next PC and memory access parameters. The CPU commits those effects and issues memory requests. RV32I arithmetic wraps at 32 bits.

Quantum instructions pass through adapt_quantum() to produce a ControlOperation. Both decoding paths run within the CPU edge.

Objects and state#

Object or member

Representation

Role

Decoded

value record

Operation, original word, register fields, immediate and register-use flags.

Effect

value record

Next PC, result, memory request parameters and branch outcome.

C++ API.

Reset and errors#

Invalid or unsupported encodings raise IllegalInstruction. The ISA library retains no state to reset.

The CPU model intercepts the exit ECALL; other ECALLs and EBREAK produce distinct traps. It delays a speculative instruction’s fault until that instruction becomes oldest, so a taken branch can discard a wrong-path fault.

Implementation and tests#

Source: isa.cpp and isa.hpp.

CTest: core.isa_arithmetic, core.isa_control, core.isa_decode, cpu.trace.

The ISA tests check arithmetic results, branch and jump effects, and the acceptance or rejection of individual instruction encodings. cpu.trace checks pipeline visibility and exit statuses 0, 1, 2 and 63 in both CPU models.